IS61DDB21M36A
Description
The 36Mb IS61DDB21M36A and IS61DDB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus.
Key Features
- 1Mx36 and 2Mx18 configuration available.
- On-chip delay-locked loop (DLL) for wide data valid window.
- Common I/O read and write ports.
- Synchronous pipeline read with self-timed late write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two input clocks (C and C#) for data output control.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
