IS61DDB21M36A Datasheet PDF (36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM) | Download Integrated Silicon Solution IS61DDB21M36A

IS61DDB21M36A - 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61DDB21M36A, a member of the IS61DDB22M18A 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM family.

Description

The 36Mb IS61DDB21M36A and IS61DDB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Features

1Mx36 and 2Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two input clocks (C and C#).

Datasheet Details

Part number	IS61DDB21M36A
Manufacturer	Integrated Silicon Solution
File Size	580.13 KB
Description	36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
Datasheet	IS61DDB21M36A Datasheet
Additional preview pages of the IS61DDB21M36A datasheet.

📁 Similar Datasheet

IS61DDB22M36C - 72Mb DDR-II CIO SYNCHRONOUS SRAM (ISSI)

IS61DDB24M18C - 72Mb DDR-II CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B21M36C - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B21M36C1 - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B21M36C2 - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B22M18C - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B22M18C1 - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B22M18C2 - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B41M18C - 18Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B41M18C1 - 18Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

Full PDF Text Transcription

Click to expand full text

IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.  HSTL input and output interface.

Published: Jul 25, 2016 |